Japanese Patent Application Laid-Open Publication No. 2003-249649 (Patent Document 1) describes a technology for suppressing the formation of interface oxide layers on and below a gate insulating film while using a high-dielectric-constant material as the gate insulating film. Concretely, a gate insulating film is formed on a semiconductor layer, and a gate electrode is formed on this gate insulating film. At this time, the gate insulating film is made of an oxide containing a metal and is formed so that the content of nitrogen or aluminum is higher at both end portions of the gate insulating film in a gate length direction than that of a central portion.
Japanese Patent Application Laid-Open Publication No. 2007-208160 (Patent Document 2) describes a technology for improving the reliability of a MISFET using a gate insulating film including a high-dielectric-constant film. Concretely, in a MISFET with a gate length of 10 nm or less, a stacked film of a silicon oxide film and a high-dielectric-constant film is used as a gate insulating film formed on a silicon substrate. At this time, the gate insulating film is formed so as to contain more nitrogen in lateral side portions than a central portion in a gate length direction and contain more nitrogen in an upper surface side than a lower surface side in a film thickness direction of the gate insulating film.
Japanese Patent Application Laid-Open Publication No. 2005-150737 (Patent Document 3) describes a technology for achieving the reliability improvement and the optimum operating characteristics in an n-channel MISFET and a p-channel MISFET, respectively. Concretely, the gate insulating film of the n-channel MISFET and the gate insulating film of the p-channel MISFET are made of different high-dielectric-constant films.